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1 datasheet 3a synchronous buck converter in 2x2 dfn package isl80030, isl80030a, is l80031, isl80031a the isl80030 , isl80030a , isl80031 and isl80031a are highly efficient, monolithic, synchronous step-down dc/dc converters that can deliver up to 3a of cont inuous output current from a 2.7v to 5.5v input supply. they use peak current mode control architecture to allow very low duty cycle operation. they operate at either a 1mhz or 2mhz switching frequency, thereby providing superior transient response and allowing for the use of small inductors. they have excellent stability. the isl80030, isl80030a, isl80031 and isl80031a integrate very low r ds(on) mosfets in order to maximize efficiency. in addition, since the high-side mosf et is a pmos, the need for a boot capacitor is eliminated, thereby reducing external component count. they can operate at 100% duty cycle. the isl80031, isl80031a configured for pfm discontinuous conduction operation, provides high efficiency by reducing switching losses at light loads. isl80030, isl80030a config ured for pwm pulse width modulation operation, provides a fast transient response, which helps reduce the output noise and rf interference. these devices are offered in a space saving 8 pin 2mmx2mm dfn lead-free package with exposed pad for improved thermal performance. the complete converter occupies less than 64mm 2 area. features ?v in range 2.7v to 5.5v ? up to 3a of output current ? switching frequency is 1mhz or 2mhz (see table 1 on page 3 ) ? 35a quiescent current (isl80031/a) ? overcurrent and short-circuit protection ? over-temperature/thermal protection ? negative current protection ? power-good and enable ? 100% duty cycle ? internal soft-start and soft-stop ?v in undervoltage lockout and v out overvoltage protection ? up to 95% peak efficiency applications ? general purpose pol ? industrial, instrumentation and medical equipment ? telecom and networking equipment ?game console figure 1. typical application circuit configuration figure 2. efficiency vs load, isl80031, v in = 5v, t a = +25c r 1 r 2 v o vfb ------------ 1 C ?? ?? = (eq. 1) vin vin en pg phase fb pgnd pgnd 1 3 2 4 8 6 7 5 vout l1 c1 22f c2 gnd vin gnd en pg isl 80030/isl80031 epad 9 +2.7v +5.5v +1.8v/3a 22f 100k ? 1% 0.6v c3 22pf r 2 r1 200k ? 1% 7 60 67 73 80 87 93 100 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 efficiency (%) v out = 1.8v v out = 2.5v load (a) v out = 3.3v caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. july 20, 2015 fn8766.0
isl80030, isl80030a, isl80031, isl80031a 2 fn8766.0 july 20, 2015 submit document feedback table of contents pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pwm control scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 pfm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 negative current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 uvlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 enable, disable and soft-start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 discharge mode (soft-stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 100% duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power derating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output inductor and capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
isl80030, isl80030a, isl80031, isl80031a 3 fn8766.0 july 20, 2015 submit document feedback table 1. summary of key differences part# pwm/pfm mode f sw (mhz) v in range (v) i out (max) (a) package size isl80030 pwm 1 2.7 to 5.5 3 8 pin 2mmx2mm dfn isl80030a pwm 2 isl80031 pfm 1 isl80031a pfm 2 note: in this datasheet, the parts in the ta ble above are collectively called "device". table 2. component value selection table v out (v) c 1 (f) c 2 (f) c 3 (pf) l 1 (h) r 1 (k ) r 2 (k ) 0.8 22 22 22 1.0~2.2 33 100 1.2 22 22 22 1.0~2.2 100 100 1.5 22 22 22 1.0~2.2 150 100 1.8 22 22 22 1.0~3.3 200 100 2.5 22 22 22 1.5~3.3 316 100 3.3 22 22 22 1.5~4.7 450 100
isl80030, isl80030a, isl80031, isl80031a 4 fn8766.0 july 20, 2015 submit document feedback pin configuration isl80030, isl80030a, isl80031, isl80031a (8 ld 2x2 dfn) top view pad 1 3 4 vin en fb 2 pgnd pgnd pg vin 7 5 6 8 phase epad (gnd) pin descriptions pin number pin name pin description 1, 2 vin the input supply for the power stage of the pwm regulator and the source for the internal linear regulator that provides bias for the ic. place a minimum of 10f ceramic capacitance from vin to gnd and as close as possible to the ic for decoupling. 3 en device enable input. when the voltage on this pin rises abov e 1.4v, the device is enabled. the device is disabled when the pin is pulled to ground. when the device is disabled, a 100 resistor discharges the ou tput through the phase pin. see figure 3 , ? functional block diagram ? on page 5 for details. 4 pg power-good output is pulled to ground during the soft-start interval and also when the output voltage is below regulation limits. there is an internal 5m internal pull-up resistor on this pin. 5 fb feedback pin for the regulator. fb is the negative input to the voltage loop error amplifier. the output voltage is set by an external resistor divider connected to fb. in addition, the power-good pwm regulator?s power-good and undervoltage protection circuits use fb to monitor the output voltage. 6, 7 pgnd power and analog ground connections. connect directly to the board ground plane. 8 phase power stage switching node for output voltage regulation. co nnect to the output inductor. this pin is discharged by an 100 resistor when the device is disabled. see figure 3 , ? functional block diagram ? on page 5 for details. - epad the exposed pad must be connected to the pgnd pin for prop er electrical performance. plac e as many vias as possible under the pad connecting to the pgnd plane for optimal thermal performance.
isl80030, isl80030a, isl80031, isl80031a 5 fn8766.0 july 20, 2015 submit document feedback functional block diagram phase + + csa + + ocp skip + + + slope comp slope soft start soft- eamp comp pwm/pfm logic controller protection hs driver fb + 0.85*vref pg shutdown vin pgnd zero-cross sensing scp + 0.3v en shutdown 1ms delay 27pf 200k 3pf 6k - - - - - - - 100 shutdown vref + neg current sensing p n + - uv 1.15*vref 5m vin bandgap figure 3. functional block diagram oscillator ov
isl80030, isl80030a, isl80031, isl80031a 6 fn8766.0 july 20, 2015 submit document feedback ordering information part number ( notes 1 , 2 , 3 ) tape and reel quantity part marking technical specifications temp. range (c) package (rohs compliant) pkg. dwg. # isl80030frz-t 1000 030 1mhz, pwm -40 to +125 8 ld dfn l8.2x2e isl80030frz-t7a 250 030 1mhz, pwm -40 to +125 8 ld dfn l8.2x2e isl80030afrz-t 1000 30a 2mhz, pwm -40 to +125 8 ld dfn l8.2x2e isl80030afrz-t7a 250 30a 2mhz, pwm -40 to +125 8 ld dfn l8.2x2e ISL80031FRZ-T 1000 031 1mhz, pfm -40 to +125 8 ld dfn l8.2x2e ISL80031FRZ-T7a 250 031 1mhz, pfm -40 to +125 8 ld dfn l8.2x2e isl80031afrz-t 1000 31a 2mhz, pfm -40 to +125 8 ld dfn l8.2x2e isl80031afrz-t7a 250 31a 2mhz, pfm -40 to +125 8 ld dfn l8.2x2e notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl80030 , isl80030a , isl80031 , isl80031a . for more information on msl please see techbrief tb363 .
isl80030, isl80030a, isl80031, isl80031a 7 fn8766.0 july 20, 2015 submit document feedback absolute maximum rating s thermal information vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v (dc) or 7v (20ms) phase . . . . . . . . . . . . . . -1.5v (100ns)/-0.3v (dc) to 6v (dc) or 7v (20ms) en, pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vin + 0.3v fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v junction temperature range at 0a . . . . . . . . . . . . . . . . . . . . . . . . . .+150c esd rating human body model ( tested per jesd22-js-001 ). . . . . . . . . . . . . . . . 4kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . 300v charged device model (tested per jesd 22-c101d) . . . . . . . . . . . . . 2kv latch-up (tested per jesd78d, clas s 2, level a). . . . 100ma at +125c thermal resistance (typical, notes 4 , 5 ) ? ja (c/w) ? jc (c/w) 2x2 dfn package . . . . . . . . . . . . . . . . . . . . 70 7 maximum junction temperature (plastic package) . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c operating junction temperature range . . . . . . . . . . . . . .-40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions v in supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 3a junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications t a = -40c to +125c, v in = 2.7v to 5.5v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the junction operat ing temperature range, -40c to +125c. parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit input supply v in undervoltage lockout threshold v uvlo rising, no load 2.5 2.7 v falling, no load 2.2 2.4 v quiescent supply current i vin isl80031a, no load at the output 35 60 a isl80030, no load at the output 7 15 ma isl80030a, no load at the output 10 22 ma shutdown supply current i sd isl80031, isl80031a, v in = 5.5v, en = low 1.2 10 a output regulation feedback voltage v fb 0.594 0.600 0.606 v t j = -40c to +125c 0.589 0.606 v vfb bias current i vfb v fb = 2.7v. t j = -40c to +125c -120 50 350 na line regulation v in = v o + 0.5v to 5.5v (minimal 2.7v) nominal = 3.6v -0.32 -0.05 0.28 %/v soft-start ramp time cycle 1ms protections positive peak current limit i plimit 3.6 4.5 5.4 a peak skip limit i skip isl80031, isl80031a v in = 3.6, v out = 1.8v (see ? applications information ? on page 17 for more detail) 450 ma zero cross threshold isl80031, isl80031a -170 -70 30 ma negative current limit i nlimit -2.6 -2 -1 a thermal shutdown temperature rising 150 c thermal shutdown hysteresis temperature falling 25 c
isl80030, isl80030a, isl80031, isl80031a 8 fn8766.0 july 20, 2015 submit document feedback compensation error amplifier transconductance 40 a/v transresistance rt 0.20 0.25 0.30 phase p-channel mosfet on-resistance v in = 5v, i o = 200ma 70 m n-channel mosfet on-resistance v in = 5v, i o = 200ma 60 m phase maximum duty cycle 100 ? phase minimum on-time isl80030; isl80030a 60 80 ns oscillator nominal switching frequency f sw isl80030, isl80031 850 1000 1150 khz isl80030a, isl80031a 1700 2000 2300 khz pg output low voltage 1ma sinking current 0.3 v delay time (rising edge) 0.5 1 2 ms pgood delay time (falling edge) 5s pg pin leakage current pg = v in 0.01 0.1 a ovp pg rising threshold 110 117 125 % ovp pg hysteresis 2% uvp pg rising threshold 80 85 90 % uvp pg hysteresis 2% en logic logic input low 0.4 v logic input high 1.4 v logic input leakage current i en pulled up to 5.5v 0.1 1 a notes: 6. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and are not production tested. electrical specifications t a = -40c to +125c, v in = 2.7v to 5.5v, unless otherwise noted. typical values are at t a = +25c. boldface limits apply across the junction operating temperature range, -40c to +125c. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
isl80030, isl80030a, isl80031, isl80031a 9 fn8766.0 july 20, 2015 submit document feedback typical performance curves figure 4. efficiency vs load (isl80031a) f sw = 2mhz, v in = 3.3v, pfm, t a = +25c figure 5. efficiency vs load (isl80030a) f sw = 2mhz, v in = 3.3v, pwm, t a = +25c figure 6. efficiency vs load (isl80031) f sw = 1mhz, v in = 3.3v, pfm, t a = +25c figure 7. efficiency vs load (isl80030) f sw = 1mhz, v in = 3.3v, pwm, t a = +25c figure 8. efficiency vs load (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c figure 9. efficiency vs load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c 60 67 73 80 87 93 100 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 efficiency (%) load (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v 40 50 60 70 80 90 100 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 efficiency (%) load (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v 60 67 73 80 87 93 100 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 efficiency (%) load (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v 40 50 60 70 80 90 100 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 efficiency (%) load (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v 60 67 73 80 87 93 100 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 efficiency (%) load (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v 40 53 67 80 93 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 100 efficiency (%) load (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v
isl80030, isl80030a, isl80031, isl80031a 10 fn8766.0 july 20, 2015 submit document feedback figure 10. efficienc y vs load (isl80031) f sw = 1mhz, v in = 5v, pfm, t a = +25c figure 11. efficiency vs load (isl80030) f sw = 1mhz, v in = 5v, pwm, t a = +25c figure 12. v out regulation vs load (isl80031) f sw = 1mhz, v out = 1.8v, pfm, t a = +25c figure 13. v out regulation vs load (isl80030) f sw = 1mhz, v out = 1.8v, pwm, t a = +25c figure 14. start-up at no load (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c figure 15. start-up at no load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c typical performance curves (continued) 60 67 73 80 87 93 100 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 efficiency (%) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v load (a) v out = 3.3v 40 50 60 70 80 90 100 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 efficiency (%) load (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v 1.850 1.854 1.859 1.863 1.867 1.872 1.876 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 output load (a) output voltage (v) 5v in pfm 3.3v in pfm 1.822 1.824 1.825 1.826 1.827 1.828 0 0.30.60.91.21.51.82.12.42.73.0 1.823 5v in pwm 3.3v in pwm output load (a) output voltage (v) phase 5v/div ven 5v/div pg 5v/div v out 1v/div 500s/div phase 5v/div ven 5v/div pg 5v/div v out 1v/div 500s/div
isl80030, isl80030a, isl80031, isl80031a 11 fn8766.0 july 20, 2015 submit document feedback figure 16. shutdown at no load (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c figure 17. shutdown at no load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 18. start-up at 3a load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 19. shutdown at 3a load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 20. start-up at 3a load (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c figure 21. shutdown at 3a load (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c typical performance curves (continued) 500s/div phase 5v/div ven 5v/div pg 5v/div v out 1v/div 500s/div phase 5v/div ven 5v/div pg 5v/div v out 1v/div 500s/div ven 5v/div i l 2a/div pg 5v/div v out 1v/div 500s/div ven 5v/div i l 2a/div pg 5v/div v out 1v/div 500s/div ven 5v/div i l 2a/div pg 5v/div v out 1v/div 1ms/div ven 5v/div i l 2a/div pg 5v/div v out 1v/div
isl80030, isl80030a, isl80031, isl80031a 12 fn8766.0 july 20, 2015 submit document feedback figure 22. start-up v in at 3a load (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c figure 23. start-up v in at 3a load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 24. shutdown v in at 3a load (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c figure 25. shutdown v in at 3a load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 26. start-up v in at no load (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c figure 27. start-up v in at no load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c typical performance curves (continued) v in 5v/div i l 2a/div pg 5v/div v out 1v/div 500s/div v in 5v/div i l 2a/div pg 5v/div v out 1v/div 500s/div phase 5v/div v in 5v/div pg 5v/div v out 1v/div 100s/div phase 5v/div v in 5v/div pg 5v/div v out 1v/div 20s/div phase 5v/div v in 5v/div pg 5v/div v out 1v/div 500s/div phase 5v/div pg 5v/div v out 1v/div 500s/div v in 5v/div
isl80030, isl80030a, isl80031, isl80031a 13 fn8766.0 july 20, 2015 submit document feedback figure 28. shutdown v in at no load (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c figure 29. shutdown v in at no load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 30. jitter at no load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 31. jitter at full load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 32. steady state at no load (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c figure 33. steady state at no load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c typical performance curves (continued) phase 5v/div v in 5v/div pg 5v/div v out 1v/div 5ms/div phase 5v/div v in 5v/div pg 5v/div v out 1v/div 2ms/div 10ns/div phase 1v/div 10ns/div phase 1v/div 50ms/div phase 5v/div i l 0.5a/div v out 20mv/div 200ns/div phase 5v/div i l 0.5a/div v out 10mv/div
isl80030, isl80030a, isl80031, isl80031a 14 fn8766.0 july 20, 2015 submit document feedback figure 34. steady state at 3a load (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c figure 35. steady state at 3a load (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 36. load transient (isl80031a) f sw = 2mhz, v in = 5v, pfm, t a = +25c figure 37. load transient (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 38. output shor t-circuit (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 39. overcurrent protection (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c typical performance curves (continued) 500ns/div phase 5v/div v out 10mv/div i l 2a/div 500ns/div phase 5v/div v out 10mv/div i l 2a/div 200s/div v out ripple 50mv/div i l 1a/div 200s/div v out ripple 50mv/div i l 1a/div phase 5v/div i l 2a/div pg 5v/div v out 1v/div 5s/div i l 2a/div pg 5v/div v out 1v/div 500s/div
isl80030, isl80030a, isl80031, isl80031a 15 fn8766.0 july 20, 2015 submit document feedback theory of operation the device is a step-down switching regulator optimized for battery powered applications. it operates at a high switching frequency (1mhz or 2mhz), which enables the use of smaller inductors resulting in small form factor, while also providing excellent efficiency. the quiescent current is typically only 1.2a when the regulator is shut down. pwm control scheme the isl80030, isl80030a employ the current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse current limiting. see ? functional block diagram ? on page 5 . the current loop consists of the oscillator, the pwm comparator, current sensing circuit and the slope compensation for the current loop stability. the slope compensation is 900mv/ts, which changes with frequency. the gain for the current sensing circuit is typically 250mv/a. the control reference for the current loop comes from the error amplifier's (eamp) output. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp-up. when the sum of the current amplifier cs a and the slope compensation reaches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-fet and turn on the n-channel mosfet. the n-fet stays on until the end of the pwm cycle. figure 42 shows the typical operating waveforms during the pwm operatio n. the dotted lines illustrate the sum of the slope compensati on ramp and the current-sense amplifier?s csa output. the reference voltage is 0.6v, which is used by feedback to adjust the output of the error amplifier, v eamp . the error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. the voltage loop is internally compensated with the 27pf and 200k rc network. the maximum eamp voltage output is precisely clamped to 1.6v. pfm operation the isl80031, isl80031a employs a pulse-skipping mode to minimize the switching loss at light load by reducing the switching frequency. figure 43 on page 16 illustrates the skip-mode operation. a zero-c ross sensing circuit shown in figure 43 monitors the n-fet current for zero crossing. when 16 consecutive cycles of the inductor current crossing zero are detected, the regulator enters the skip mode. during the eight detecting cycles, the current in th e inductor is allowed to become negative. the counter is reset to zero when the current in any cycle does not cross zero. figure 40. overvoltage protection (isl80030a) f sw = 2mhz, v in = 5v, pwm, t a = +25c figure 41. over-temperature protection f sw = 2mhz, v in = 5v, pwm, t a = +150c typical performance curves (continued) phase 5v/div i l 2a/div pg 5v/div v out 2v/div 200s/div pg 2v/div v out 0.5v/div 1ms/div figure 42. pwm operation waveforms v eamp v csa duty cycle i l v out
isl80030, isl80030a, isl80031, isl80031a 16 fn8766.0 july 20, 2015 submit document feedback once the skip mode is entered, the pulse modulation starts being controlled by the skip comparator as shown in the ? functional block diagram ? on page 5 . each pulse cycle is still synchronized by the pwm clock. the p-fet is tu rned on at the clock's rising edge and turned off when the output is higher than 1.5% of the nominal regulation or when its current reaches the peak skip current limit value. then the inductor current discharges to 0a and stays at zero. the internal clock is disabled. the output voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the nominal voltage, the p-fet will be turned on again at the rising edge of the internal clock as it repe ats the previous operations. overcurrent protection the overcurrent protection is realized by monitoring the csa output with the ocp comparator, as shown in the ? functional block diagram ? on page 5 . the current sensing circuit has a gain of 300mv/a, from the p-fet current to the csa output. when the csa output reaches a threshold, the ocp comparator is tripped to turn off the p-fet immediately. the overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper mosfet. upon detection of overcurrent condition, the upper mosfet will be immediately turned off and will not be turned on again until the next switching cycle. if the overcurrent condition goes away, the output will resume back into the regulation point. short-circuit protection the short-circuit protection (scp) comparator monitors the vfb pin voltage for output short-circ uit protection. when the vfb is lower than 0.3v, the scp comparat or forces the pwm oscillator frequency to drop to 1/3 of the normal operation value. this comparator is effective during start-up or an output short-circuit event. negative current protection similar to the overcurrent, the ne gative current protection is realized by monitoring the current across the low-side n-fet, as shown in the ? functional block diagram ? on page 5 . when the valley point of the inductor current reaches -2a for 2 consecutive cycles, both p-fet and n-fet shut off. the 100 in parallel to the n-fet will activate discharging the output into regulation. the control will begin to switch when output is within regulation. the regulator will be in pfm for 20s before switching to pwm if necessary. pg pg is an output of a window comp arator that continuously monitors the buck regulator output voltage. pg is actively held low when en is low and during the buck regulator soft-start period. after 1ms delay of the soft-start period, pg become s high impedance as long as the output voltage is within nominal regulation voltage set by vfb. when vfb drops 15% below or raises 15% above the nominal regulation voltage, the device pulls pg low. any fault condition forces pg low until the fault condition is cleared by attempts to soft-start. there is an internal 5m pull-up resistor to fit most applications. an external resistor can be added from pg to vin for more pull-up strength. uvlo when the input voltage is below the undervoltage lockout (uvlo) threshold, the regulator is disabled. enable, disable and soft-start up after the vin pin exceeds its rising por trip point (nominal 2.5v), the device begins operation. if the en pin is held low externally, nothing happens until this pin is released. once the en is released and above the logic th reshold, the internal default soft-start time is 1ms. discharge mode (soft-stop) when a transition to shutdown mode occurs or the vin uvlo is set, the outputs discharge to gnd through an internal 100 switch. 100% duty cycle the device features 100% duty cycle operation to maximize the battery life. when the battery voltage drops to a level that the device can no longer maintain th e regulation at the output, the regulator completely turns on the p-fet. the maximum dropout voltage under the 100% duty cycle operation is the product of the load current and the on-resistance of the p-fet. clock i l v out nominal +1.5% nominal pfm current limit 0 16 cycles pwm pfm nominal -1.5% pwm load current figure 43. pfm mode operation waveforms
isl80030, isl80030a, isl80031, isl80031a 17 fn8766.0 july 20, 2015 submit document feedback thermal shutdown the device has built-in thermal protection. when the internal temperature reaches +150c, the regulator is completely shut down. as the temperature drops to +125c, the device resumes operation by stepping through the soft-start. power derating characteristics to prevent the device from ex ceeding the maximum junction temperature, some thermal analysis is required. the temperature rise is given by equation 2 : where pd is the power dissipated by the regulator and ja is the thermal resistance from the junc tion of the die to the ambient temperature. the junction temperature, t j , is given by equation 3 : where t a is the ambient temperature. for the dfn package, the ja is +70c/w. the actual junction temperature should not exceed the absolute maximum junction temperature of +125c when considering the thermal design. the device delivers full current at ambient temperatures up to +85c; if the thermal impeda nce from the thermal pad maintains the junction temperat ure below the thermal shutdown level, depending on the input voltage/output voltage combination and the switching frequency. the device power dissipation must be reduced to maintain the junction temperature at or below th e thermal shutdown level. figure 44 illustrates the approximate output current derating versus ambient temperature for the isl80030eval1z board. applications information output inductor and capacitor selection to consider steady state and transient operations, the device typically requires a 1h output inductor. higher or lower inductor values can be used to optimize the total converter system performance. for example, for higher output voltage 3.3v application, in order to decrease the inductor ripple current and output voltage ripple, the output inductor value can be increased. it is recommended to set the inductor ripple current to be approximately 30% of the maximu m output current for optimized performance. the inductor ripple current can be expressed as shown in equation 4 : the inductor?s saturation current rating needs to be at least larger than the peak current. the device uses an internal compensation network and the output capacitor value is dependent on the output voltage. the ceramic capacitor is recommended to be x5r or x7r. output voltage selection the output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. the output voltage programming resistor, r 1 , will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. the value for the feedback resistor is typically between 10k and 100k ?? as shown in equation 5 . if the output voltage desired is 0.6v, then r 2 is left unpopulated and r 1 is shorted. there is a leakage current from vin to lx. it is recommended to preload the output with 10a minimum. for better performance, add 22pf in parallel with r 1 ?? input capacitor selection the main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. at least two 22f x5r or x7r ceramic capacitors are a good starting point for th e input capacitor selection. output capacitor selection an output capacitor is required to filter the inductor current. output ripple voltage and transi ent response ar e two critical factors when considering output capacitance choice. the current mode control loop allows for the usage of low esr ceramic capacitors and thus smaller bo ard layout. electrolytic and polymer capacitors may also be used. additional consideration applies to ceramic capacitors. while they offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. ceramic capacitors t rise pd ??? ja ?? = (eq. 2) t j t a t rise + ?? = (eq. 3) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 50 60 70 80 90 100 110 120 130 temperature (c) v in = 5v, olfm figure 44. derating curve vs temperature output current (v) ? i v o 1 v o v in --------- C ?? ?? ?? ? lf sw ? -------------------------------------- - = (eq. 4) r 1 r 2 v o vfb ------------ 1 C ?? ?? = (eq. 5)
isl80030, isl80030a, isl80031, isl80031a 18 fn8766.0 july 20, 2015 submit document feedback are rated using large peak-to-peak voltage swings and with no dc bias. in the dc/dc converter applic ation, these conditions do not reflect reality. as a result, the actual capacitance may be considerably lower than the ad vertised value. consult the manufacturers datasheet to determine the actual in-application capacitance. most manufacturers publish capacitance vs dc bias so this effect can be easily accommodated. the effects of ac voltage are not frequently publis hed, but an assumption of ~20% further reduction will generally suffice. the result of these considerations can easily result in an effective capacitance 50% lower than the rated value. nonetheless, they are a very good choice in many applications due to their reliability and extremely low esr. the following equations allow calculation of the required capacitance to meet a desired ripple voltage level. additional capacitance may be used. for the ceramic capacitors (low esr) = where ? i is the inductor?s peak-to-peak ripple current, f sw is the switching frequency and c out is the output capacitor. if using electrolytic capacitors then: regarding transient response needs, a good starting point is to determine the allowable overshoot in v out if the load is suddenly removed. in this case, energy stored in the inductor will be transferred to c out causing its voltage to rise. after calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. the following equation determines the required output capacitor value in order to achieve a desired overshoot relative to the regulated voltage. where v outmax /v out is the relative maximum overshoot allowed during the removal of the load. for an overshoot of 5%, equation 9 becomes as follows: layout considerations the pcb layout is a very important converter design step to make sure the designed converter works well. the power loop is composed of the output inductor l?s, the output capacitor c out , the phase?s pins and the pgnd pin. it is necessary to make the power loop as small as possibl e and the connecting traces among them should be direct, short and wide. the switching node of the converter, the phase pins and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. the input capacitor should be placed as closely as possible to the vin pin and the ground of the input and output capacitors should be connected as closely as possible. the heat of the ic is mainly dissipated through the thermal pad. maximizing the copper area connected to the thermal pad is preferable. in addition, a solid ground plane is helpful for better emi performance. it is recommended to add at least 4 vias ground connection within the pad for the best thermal relief. v outripple ? i 8 ? f sw ? c out ------------------------------------ - = (eq. 6) v outripple ? i*esr = (eq. 7) (eq. 8) c out i out 2 * l v out 2 * v outmax v out ? ?? 2 1 ? C --------------------------------------------------------------- ----------------------------- = c out i out 2 * l v out 2 * 1.05 ? 2 1 ? C ----------------------------------------------------- = (eq. 9)
isl80030, isl80030a, isl80031, isl80031a 19 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8766.0 july 20, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change july 20, 2015 fn8766.0 initial release
isl80030, isl80030a, isl80031, isl80031a 20 fn8766.0 july 20, 2015 submit document feedback package outline drawing l8.2x2e 8 lead dual flat no-lead plastic package (dfn) with e-pad rev 0, 5/15 located within the zone indicate d. the pin #1 identifier may be unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 2.00 2.00 (6x0.50) 2.00 2.00 (8x0.30) (8x0.20) ( 8x0.30 ) 0.50 0.800.050 exp.dap 0.25 1.450.050 exp.dap (8x0.25) 0.80 1.45 pin #1 index area b 0.10 m a c 0.90 0.10 c seating plane base plane 0.08 0.10 see detail "x" c c 0.00 min. 0.05 max. 0.2 ref c 6 index area pin 1 6 (4x) 0.15 a b 1 package outline 8

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